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● UCI · High-frequency Integrated Electronics Lab

You give it a PLL specification. It gives back a sized netlist.

High-frequency Integrated Electronics Lab · EECS · University of California, Irvine

You state what the loop must do. Each block has candidate topologies, each with a trained model and a region it is valid in. The selector picks one, inverse design turns the target into a sizing, and Spectre checks it.

Verified blocks are composed with their uncertainty carried through — error bars on the whole loop, not on the parts. Out comes a sized netlist, run as one transistor-level circuit in Spectre. It locks, and it holds.

FOR EACH BLOCK OF THE LOOPSpecificationwhat the loop must do,split into per-block targetsTopology selectioncandidates + valid regionForward modeltrained per topologyInverse designspec → sizingSpectre checkon its own testbenchCompositionuncertainty propagatedNetlist + sizingthe whole PLL, every deviceAssembled loop in Spectretransistor level — it locks, and holdsmeasured error feeds back into the model
Fig. 1 The workflow. Everything inside the dashed band happens once per block. Generating the data and training the models is upstream of all of it — once per topology, not once per design. Composition is where the loop appears: each model’s uncertainty is propagated through it, so the error bars are on the whole loop and not just on the blocks. Only then is the assembled circuit run at transistor level.
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§ 01What happens

Four steps, and the fourth one is the reason the other three are worth doing.

Sizing one cell well is a solved-enough problem. Choosing which topology each block should be, sizing all of them so that the loop they form meets a specification, and knowing how wrong the answer might be once they are attached to each other — that is not.

  1. 01

    You state the specification

    What the loop has to do, as numbers inside published ranges: output frequency, phase noise, lock time, power budget, the reference you are locking to. Never a file and never code — nothing you supply is executed anywhere.

  2. 02

    A topology is chosen, then its model is inverted

    A block is not one circuit. Each has a library of candidate topologies, and each of those carries its own dataset, its own forward model trained on it, and its own validated region — so the choice between them is made on measured evidence rather than on habit, and outside a model’s validated region the answer is a refusal rather than a guess. Inverse design then runs the chosen topology’s forward model backwards, from the target specification to a sizing.

  3. 03

    Each proposal is checked in Spectre, and the error feeds back

    One block, one testbench, against a production foundry PDK. A proposal is not a result until the simulator has measured it, and the gap between what the model predicted and what the simulator measured goes back into the model rather than into a footnote.

  4. 04

    The blocks are composed, and the assembled loop is run

    This is the step that makes it a PLL and not a set of exercises. The verified blocks are combined — every boundary between two of them is itself a designed, characterised cell — and each model’s uncertainty is propagated through the composition, so what comes out carries error bars on the whole loop rather than on the parts. The result is a netlist for the whole PLL with every device sized, assembled and run as one transistor-level circuit in Spectre: it locks, and it holds.

§ 02The loop

The chain, and the seams between its links.

This is the object the method is applied to. Each block is a design problem with its own topologies, its own measurements and its own way of failing — and between every two of them sits another designed cell, which is why the feedback path is four blocks and not one wire.

ReferencePhase detectorCharge pumpLoop filterOscillatorCoupler + bufferDivider chainLevel converterFeedback dividerto the output▬ every boundary between blocks is itself a designed, characterised cell
Fig. 2 The loop. The marks on the wires are not decoration: every boundary between two blocks is itself a designed, characterised cell, and the seams are where a loop assembled from separately-designed blocks fails.
Table 1 · The blocks of Fig. 2, in signal order
BlockFunction in the loop
ReferenceSquares the crystal into the clean edge everything else is timed against.
Phase detectorCompares the reference edge against the feedback edge, and says which one is early.
Charge pumpTurns that comparison into charge delivered onto the filter.
Loop filterHolds the tuning voltage, and sets the loop bandwidth and the phase margin.
OscillatorTurns that voltage into the output frequency. Everything else exists to steer it.
Coupler + bufferA designed take-off: samples the oscillator for the feedback path without loading it.
Divider chainBrings the output down to a rate the rest of the feedback path can work at.
Level converterCarries edges between the supply and logic domains the two halves run in.
Feedback dividerDivides the rest of the way to the reference rate, ready to be compared again.

The loop filter is a passive network, solved on paper and confirmed in simulation; there is nothing in it for a learned model to be wrong about. The rest of the die — bias and decoupling, the scan chain that carries the control bits, the output path and the top-level assembly — is designed and verified in the ordinary way.

§ 03Why it is hard

A predicted number without a measured band is not a design input.

A digital block is compiled. An analog block is negotiated — sized by hand, checked, resized, until the corner that matters stops failing. Six blocks in one loop is six times that problem, plus the problem of making them agree at the interfaces.

A learned model can carry part of it, but only if its error is stated where the design actually sits. A band pooled over a whole operating range flatters the region the model found easy and libels the region it found hard, so a single figure of merit can be wrong in both directions at once.

So a band here is cut by operating point, and a region with too few points is recorded as unproven rather than allowed to borrow a wider one. Where a band cannot separate two candidates, the model is used to screen and not to select — recorded as such, rather than promoted because a headline accuracy looked good.

And every requirement is re-checked in the simulator before anything is reported. What comes back is a design the simulator has already agreed to, with the residual disagreement stated rather than smoothed over.

§ 04A run

What a single run does, in six stages.

The stage names are the worker’s own — the strings it prints while a run is in flight — so the description here and the progress a signed-in visitor watches use the same words.

  1. Specification

    spec_input

    The quantities the block is asked to hit, as numbers inside published ranges — never a file, never code.

  2. Inverse design

    inverse_design

    A learned forward model is inverted under constraint to propose device sizing, then its own calibration moves the prediction by the error band measured for that operating bin.

  3. Netlist render

    netlist_render

    A lab-authored template renders the deck. Parameters are bounds-checked numbers; nothing supplied from outside is interpolated into a simulator input.

  4. Spectre verify

    spectre_verify

    The candidate block is simulated on its own testbench against the real foundry PDK, under a CPU and wall-clock ceiling, one job at a time so the department’s licence seats are never contended.

  5. Extract

    extract

    Heads are measured from the simulation, not read back from the model. A head the loop cannot check is reported as unchecked.

  6. Rank

    rank_result

    Candidates are ranked by measured margin against every gate. What returns to the browser is metrics and plots — nothing else.

§ 05Demo

Request a demo.

A demo is a real run, not a recording: you state a specification, the model proposes a sizing, and the simulator answers on the lab’s own machine while the six stages go by. Because that machine holds a production PDK under NDA, accounts are issued by the lab rather than by a form — there is no sign-up.

  1. Step 01

    You ask

    The request form records who you are and what you want to run. It creates nothing and grants nothing.

  2. Step 02

    The lab clears you with the foundry

    The demo runs against a real production PDK under NDA. Clearance is a manual, out-of-band conversation and takes days, not minutes.

  3. Step 03

    The lab issues an account

    Only after clearance. Sign-in is an emailed link — there is no password, and there is no way to register yourself.

Request a demoAlready have an account →