● UCI · High-frequency Integrated Electronics Lab
The model proposes.
Spectre decides.
A closed loop for analog and RF integrated-circuit design. You state a specification; a learned model is inverted to propose device sizing; a lab-authored template renders the netlist; and a real foundry PDK is simulated before a single number is reported.
- 200 / 200
- proposals became netlists that simulated
- 72
- closed-loop points behind the shipping topology
- 40 / 40
- of its designs met every gate in Spectre
- +0.77 %
- median error out of sample, against +8.6 % uncalibrated
Analog design does not scale
the way digital does.
A digital block is compiled. An analog block is negotiated — sized by hand, checked, resized, until the corner that matters stops failing. The judgement that makes that fast lives in a handful of people, and it does not transfer.
A learned model can carry some of it. But a predicted pump current with an unstated error band is a guess wearing a decimal point, and a benchmark that reports only its successes has not told you where it breaks.
So this workflow does two things a benchmark does not. Every prediction is moved by the error measured for the operating point it sits in — never a pooled band borrowed from a range it was not measured on. And every gate is re-checked in a simulator before anything is reported at all.
What comes back is not the model’s opinion of a design. It is a design the simulator has already agreed to, with the residual disagreement stated.
“nviol = 0 is the model’s opinion. Reachability is a measurement.”
Six stages, and one of them is a simulator.
The stage names below are the worker’s own — the strings it prints while a run is in flight. A signed-in visitor watches the same six go by.
Specification
spec_inputPump current, compliance window, power budget. Numbers inside published ranges — never a file, never code.
Inverse design
inverse_designA learned forward model is inverted under constraint to propose device sizing, then its own calibration moves the prediction by the error band measured for that operating bin.
Netlist render
netlist_renderA lab-authored template renders the deck. Parameters are bounds-checked numbers; nothing supplied from outside is interpolated into a simulator input.
Spectre verify
spectre_verifyThe candidate is simulated against the real foundry PDK, under a CPU and wall-clock ceiling, one job at a time so the department’s licence seats are never contended.
Extract
extractHeads are measured from the simulation, not read back from the model. A head the loop cannot check is reported as unchecked.
Rank
rank_resultCandidates are ranked by measured margin against every gate. What returns to the browser is metrics and plots — nothing else.
What was actually run.
Four charge-pump topologies, 200 proposals, every one of them carried through to a simulation. The first version ships on one of the four; the other three are published because their failures are the useful part.
| Topology | Spec inputs | Closed-loop points | Met every gate | Verdict |
|---|---|---|---|---|
csv1 | 8 | 72 | 40 / 40 | Every specification window reached. The rail v1 ships on. |
ncc | 5 | 48 | 18 / 40 | Fine to 62 µA, then static phase offset misses its gate on every design. |
sl | 5 | 48 | 18 / 40 | Undershoots the requested pump current on every specification tried. |
diff | 5 | 48 | 15 / 40 | Cannot reach mid-band current inside its power budget — a circuit limit, not a model one. |
All 200 proposals became netlists that simulated — the inverse → emitter → simulator chain never failed once. Calibration then removes the slope a piecewise-constant learner extrapolates with: on the shipping topology the pump-current band falls from 10.34 % to 5.31 %, and an out-of-sample window with no hand-set margin came back at a median +0.77 %.
What it does not promise.
An error band means little beside the heads it does not cover. These are published at the same weight as the results, because a workflow that only prints its successes has not told you anything you can plan around.
- Limit 01
No noise claim comes out of this loop.
Output-current noise is not in the proposals’ prediction set, so the closed loop never checks it. There is no evidence for it here, and none is reported.
- Limit 02
One topology’s phase-offset band is wider than its own gate.
On the ncc rail the static phase offset carries a 110 ps band against a ±100 ps limit. A correction reaches roughly 40 ps at best, so the band cannot police the window. It needs different features or a different measurement — not a tighter claim.
- Limit 03
A calibration cannot fix what is not bias.
The sl rail’s pump-current error stays at 12.6 % after calibration: 0.8 % bias against 3.3 % scatter leaves a correction almost nothing to take.
- Limit 04
A model being right does not make a topology good.
The diff rail’s model error was fixed. Its circuit-level disadvantages — halved tune-line swing on a single-ended tap, materially worse reference spur — are independent of any model and remain.
- Limit 05
A band is quoted for an operating point, never pooled and reused.
Pump-current error on the shipping rail is 10.34 % pooled, but 2.92 % at 85–100 µA and 11.14 % at 55–70 µA. A bin with too few points reads unproven and does not borrow the wider band.
There is no sign-up.
The demo runs against a production PDK under NDA. That makes issuing an account a decision the lab takes with the foundry — days of human process, not a form that returns a password.
- 01
You ask
The form below records who you are and what you want to run. It creates nothing and grants nothing.
- 02
The lab clears you with the foundry
The demo runs against a real production PDK under NDA. Clearance is a manual, out-of-band conversation and takes days, not minutes.
- 03
The lab issues an account
Only after clearance. Sign-in is an emailed link — there is no password, and there is no way to register yourself.